Electronics Interview Questions: STA part 2


Welcome to ElectroTuts. in this video we will
continue our discussion on interview questions related to Static Timing Analysis. if you
haven’t watched the first part of the series then do watch it before proceeding. I have
attached a link for the same in description below. so let’s get started.
The question is, how can we eliminate hold time violations in a circuit? I can rephrase
the question as, what to do if hold time constraint is not satisfied in a circuit? Let’s have a look at our questions from previous
video. having a look at the hold time equations we see that, reducing hold time can do our
task of eliminating hold time violation. So one solution to this can be to reduce hold
time. So we can replace our flip flops with the flip flops having lower hold time compared
to the present one. generally this solution is not preferred. another possible way is to increase this propagation delay of combinational logic. So. increase Tpd, the delay of combinational logic block. if our circuit has delay in its clock path.
then a third way can be to reduce the buffer delay present in the clock path as it will
help to meet our hold time constraint. So decrease T buffer.Generally one of these two
methods adopted, but one should be careful as changing these parameters also have effect
on setup equation. So if not done right you can end up with setup violation instead. Now let’s move on to next question How to eliminate
setup violation. Again looking back to these equation,s we can see that increasing the
time period of the clock at which the circuit operates seems to be the most visible choice
to eliminate setup violation. So our first Method can be to increase time period. What
if we can’t touch the time period, because generally time period of a circuit is fixed
by other teams or the marketing team for a competitive product. So what we can do is
to use a flip flop with lower setup time, or reduce the propagation delay of this combinational
circuit. Or from this equation below we can see that adding a buffer in clock path will
also reduce chances of having a setup violation. So we can reduce propagation delay, or we
can also buffer in clock path. But here also care must be taken as changing these parameters
have affect on hold time constraints. Notice that for eliminating hold time violation Tpd
must be increased and for setup violation it must be decreased, similarly buffer delay
must be decreased for eliminating hold time violation and it must be added for setup time
violation. So, a compromise must be reached for these values such that both setup and
hold constraints are met, else the only choice we would be left with is to increase the clock
period at which the circuit operates. There is another way to reduce setup time constraint. this method is also used to operate
a given circuit at Higher frequencies, frequency greater than the maximum frequency possible
for a given circuit given by setup time constraint. this type of question is also asked in interviews,
like they may give you one of these questions and ask you to make the circuit operate the
frequency greater than fmax. Let’s see this using an example. this question is same as
in previous video, but we are considering delay values here. Tcq is 1ns, Tpd is 6ns, Ts is 3ns. Assuming that the hold time constraint is met, find the maximum frequency at which
this circuit can operate. Using the setup time constraint, Tcq + Tpd + Tsetup

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